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ispPAC 20
TM
In-System Programmable Analog Circuit Features
* IN-SYSTEM PROGRAMMABLE (ISPTM) ANALOG -- Two Instrument Amplifier Gain/Attenuation Stages -- Signal Summation (Up to 3 Inputs) -- Precision Active Filtering (10kHz to 100kHz) -- 8-Bit DAC and Fast Dual Comparator -- Non-Volatile E2CMOS(R) Cells (10,000 Cycles) -- IEEE 1149.1 JTAG Serial Port Programming * LINEAR ELEMENT BUILDING BLOCKS -- Programmable Gain Range (0dB to 40dB) -- Bandwidth of 550kHz (G=1), 330kHz (G=10) -- Low Distortion (THD < -74dB max @ 10kHz) -- Auto-Calibrated PACblockTM Input Offset Voltage * TRUE DIFFERENTIAL I/O -- High CMR (69dB) Instrument Amplifier Inputs -- 2.5V Common Mode Reference on Chip -- Rail-to-Rail Voltage Outputs -- Single Supply 5V Operation * 44-PIN PLASTIC PLCC PACKAGE * APPLICATIONS INCLUDE INTEGRATED: -- Single +5V Supply Signal Conditioning -- Active Filters, Gain Stages, Summing Blocks -- Analog Front Ends, 12-Bit Data Acq. Systems -- Precision Voltage Controlled Oscillator -- Synchronous Detection Circuits -- Precision Rectification & Other Non-Linear Functions
Functional Block Diagram
DACOUT+ VREFOUT DACOUT- ENSPI CMVin
MSEL
TEST
GND CAL
IN3-
6 IN3+ IN1- IN1+ OUT1- OUT1+ GND OUT2+ OUT2- IN2+ IN2- VS 7
IA
5
4
3
2
1 44 43 42 41 40 39
OA CP
VS
D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) CPIN+ CPIN- GND
8 9 10 11 12 13 14 15 16 17
Auto-Cal ISP Control E2CMOS Mem IA OA IA IA
38 37 36 35 34 33 32 31
CP
Analog Routing Pool
Reference DAC
30 29
18 19 20 21 22 23 24 25 26 27 28
TDI TMS TCK PC CS TDO DMODE VS WINDOW CP1OUT CP2OUT
Description
The ISPPAC20 is a member of the Lattice family of InSystem Programmable analog circuits, digitally configured via nonvolatile E2CMOS technology. Analog building blocks, called PACblocks, replace traditional analog components such as opamps and active filters, eliminating the need for most external resistors and capacitors. Also included are an 8-bit DAC and dual comparators. With no requirement for external configuration components, ISPPAC20 expedites the design process, simplifying prototype circuit implementation and change, while providing high-performance integrated functionality. Designers configure the ISPPAC20 and verify its performance using PAC-DesignerTM, an easy to use, Microsoft Windows(R) compatible program. Device programming is supported using PC parallel port I/O operations. The ISPPAC20 is configured through its IEEE Standard 1149.1 (JTAG) compliant serial port. The flexible In-System Programming capability enables programming, verification and reconfiguration if desired, directly on the printed circuit board.
Typical Application Diagram
5V Vin 5V 12-Bit Differential Input ADC
Ain+ Ain-
Ref+ DAC Ref-
ISPPAC20
Copyright (c) 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-888-477-7537; FAX (503) 268-8037; http://www.latticesemi.com
March 2000
pac20_03
1
Specifications ISPPAC20
TA = 25C; VS = 5.0V; Signal path = VIN to VOUT of one PACblock (second input unused); 1V VOUT 4V; Gain = 1; Output load = 200pf, 1M. Feedback enabled; Feedback capacitor = minimum; Auto-cal initiated immediately prior. (Unless otherwise specified).
DC Electrical Characteristics
SYMBOL PARAMETER CONDITION MIN. TYP. MAX. UNITS
PACblock Analog Input VIN (1) Input Voltage Range VIN-DIFF Differential Input Voltage Swing (2) VOS (2) Differential Offset Voltage (Input Referred) VOS/T RIN CIN IB eN Differential Offset Voltage Drift Input Resistance Input Capacitance Input Bias Current Input Noise Voltage Density
Applied to Either VIN+ or VIN- 2| VIN+ - VIN- | G = 10 G=1 -40 to +85C
1 6 20 0.2 50 109 2 3 38 0.1 9.6 10 2.475 0
4 100 1.0
at DC At 10kHz, Referred to Input, G = 10 Present at Either VOUT+ or VOUT- 2| VOUT+ - VOUT- | Source/Sink (VOUT+ + VOUT-)/2 ; VIN+ = VIN- Each individual PACblock RL = 300 Differential Between Two Inputs of Same PACblock -40 to +85C Differential at 1kHz Single-ended at 1kHz Nominally 2.500V Optional External VREFOUT Reference Voltage -40 to +85C Source Sink 10MHz Bandwidth; 1F Bypass Capacitor 1kHz
V Vp-p V mV V/C pF pA nV/Hz V Vp-p mA V dB % % ppm/C dB dB % V ppm/C A A VRMS dB
PACblock Analog Output VOUT Output Voltage Range VOUT-DIFF Differential Output Voltage Swing (2) IOUT Output Current VCM Common Mode Output Voltage PACblock Static Performance G Programmable Gain Range Gain Error Gain Matching G/T Gain Drift PSR Power Supply Rejection Common Mode Reference Output (VREFOUT) VREFOUT Output Voltage Range CMVIN (4) Common Mode Output Voltage Input Output Voltage Drift IREFOUT Output Current Output Noise Voltage Power Supply Rejection Digital-to-Analog Converter (DAC) PACell Resolution INL Integral Non-Linearity Error DNL Differential Non-Linearity Gain Error /T Gain Drift VOS Differential Offset Voltage VCM Common Mode Output Voltage PSR Power Supply Rejection VOS/T Differential Offset Voltage Drift FSR Differential Full Scale Range VOUT Voltage Output Range IOUT Output Current SR Output Slew Rate tS Output Settling Time 0.1% Temperature Range Operation Storage
4.9
2.500
2.525 26 4.0 3.0
20 80 77 -0.2 1.25 50 50 350 40 80 8 +0.2 3.25
Guaranteed Monotonic -40 to +85C (DOUT+ + DOUT-)/2 Differential at 1kHz -40 to +85C DAC Code 00h to FFh RL = 1K Differential Source/Sink 6VDIFF Input Step -40 -65 2.495 20 2.500 80 50 6.0
1 10 1.3 4.8
bits lsb lsb % ppm/C 2 mV 2.505 V dB V/C V 4 V mA V/s 6.0 s 0.5 1.0 2.5 +85 +150 C C
2
Specifications ISPPAC20
DC Electrical Characteristics (Continued)
SYMBOL
Comparator PACells AV VOS VOS/T PSR tP Voltage Gain Input Offset Voltage Differential Offset Voltage Drift Power Supply Rejection Programmable Hysteresis Propagation Delay 108 5 50 80 47 750 150 0 60 10K 0 2.0 0V TCK Input VS 0V All Other Inputs VS IOL = 4.0mA IOH = -1.0mA 0.8 VS 10 +40/-70 0.5 5.0 dB mV V/C dB mV ns ns V dB cycles V V A A V V V mA mW
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNITS
-40 to +85C Differential at 1kHz On or Off Overdrive = 10mV Overdrive = 100mV
Input Common Mode Input Range CMRR Input Common Mode Rejection Ratio Programming Erase Program Cycles Digital I/O VIL Input Low Voltage VIH Input High Voltage IIL, IIH Input Leakage Current VOL (5) VOH (5) Power Supplies VS IS PD Output Low Voltage Output High Voltage Operating Supply Voltage Supply Current Power Dissipation
2.4 4.75 5.0 5.25 21 105
VS = 5.0V VS = 5.0V
AC Electrical Characteristics
SYMBOL PARAMETER CONDITION
FIN = 10kHz FIN = 100kHz 0.1Hz to 100kHz 10kHz 100kHz
MIN.
TYP.
-88 -72 -67 -63 103 69 55 550 330 330 7.5 2.0 -90
MAX.
-74 -62
UNITS
dB dB dB dB dB dB dB kHz kHz kHz V/s s dB kHz % % %/C
PACblock Dynamic Performance THD Total Harmonic Distortion
Differential Single-Ended Differential Single-Ended SNR Signal to Noise G = 1 to 10 CMR Common Mode Rejection (VIN = 1V to 4V) Note: VIN+ and VIN- connected together BW Small Signal Bandwidth G=1 G = 10 BWFP Full Power Bandwidth SR Slew Rate tS Settling Time 0.1% Crosstalk PACell Filter Characteristics Filter Pole Programming Range F0 Absolute Pole Frequency Accuracy F0 Pole Step Size (Between Calculated Poles) DF0/DT Pole Frequency Change vs. Temperature
VIN = 6VDIFF, VOUT = -3dB, G=1 5.0 6VDIFF Input Step Between Any Two Channels Number of Poles in Range > 120 Deviation From Calculated Value 10kHz to 100kHz -40 to +85C 10
1.0 0.02
100 5.0 3.2
Notes: (1) A wider input range of 0.7V to 4.3V is typical, but not guaranteed. Inputs larger than this will be clipped. Input signals are also subject to common-mode voltage limitations. Refer to the table of conditions in this datasheet. (2) Refer to theory of operation section later in this datasheet for explanation of differential voltage swing computation. (3) To insure full spec performance an additional auto-calibration should be performed after initial turn-on and the device reaches thermal stability.(4) The user-provided voltage on this pin (CMVIN) becomes an optional (selected via programming) alternative to the default 2.5V VREFOUT. (5) Includes TDO, CP1OUT, CP2OUT and WINDOW output logic pins.
3
Specifications ISPPAC20
Absolute Maximum Ratings
Supply Voltage VS ....................................... -0.5 to +7V Logic and Analog Input Voltage Applied ........... 0 to VS Logic and Analog Output Short Circuit Duration ..... Indefinite Lead Temperature (Soldering, 10 sec.) .............. 260C Ambient Temperature with Power Applied ... -55 to 125C Storage Temperature ................................ -65 to 150C Note: Stresses above those listed may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied.
Package Options
ISPPAC20
44-Pin PLCC
Part Number Description
ispPAC 20 - XX X X Device Family Device Number Performance Grade 01 = Standard Package J = PLCC Grade Blank = Commercial I = Industrial Temperature
ISPPAC20 Ordering Information
Ordering Number ISPPAC20-01JI Package 44-Pin PLCC
4
Specifications ISPPAC20
Timing Specifications (JTAG Interface Mode)
TA = 25C; VS = +5.0V (Unless otherwise specified) SYMBOL PARAMETER CONDITION MIN. TYP. MAX. UNITS
Dynamic Performance tckmin Minimum Clock Period tckh TCK High Time tckl TCK Low Time tmss TMS Setup Time tmsh TMS Hold Time tdis TDI Setup Time tdih TDI Hold Time tdozx TDO Float to Valid Delay tdov TDO Valid Delay tdoxz TDO Valid to Float Delay tpwp Time for a programming operation tpwe Time for an erase operation tpwcal1 Time for auto-cal operation on power-up tcalmin Minimum auto-cal pulse width tpwcal2 Time for user initiated auto-cal operation
200 50 50 15 10 15 10 60 60 60 100 100 250 100
Executed in Run-Test/Idle Executed in Run-Test/Idle Automatically executed at power-up Executed on rising edge of CAL
80 80 40
ns ns ns ns ns ns ns ns ns ns ms ms ms ns ms
tckh TCK tmss tmsh
tckl
tckmin
tpwp, tpwe TCK tmss *(PRGUSR/UBE executed in Run-Test/Idle state) tmss
TMS tdis tdih
TMS
TDI tdozx tdov tdoxz
CAL tcalmin
(Note: CAL internally initiated at device turn-on.)
VOUT = 0VDIFF
TDO
VOUT tpwcal1, tpwcal2
*Note: During device JTAG programming, filsum PACblock analog outputs will stop responding to normal input stimulus. This is because all configuration information is erased and then re-written as part of a normal programming cycle, momentarily disrupting the input to output signal path. Behavior is not predictable during either of these steps since the analog outputs are not clamped during a programming cycle. Usually, however, the outputs will slew to either 0V (Ground) or 5V (Vsupply) or 2.5V (VREFOUT). This behavior is partially determined by conditions existing immediately prior to device reprogramming and intermediate configurations that occur during the process. DAC outputs will go to -FS (-3VDIFF) during bulk erase and then to +FS (+3VDIFF) for less than 2ms during final programming before assuming the programmed code value. Comparator outputs can change due to a number of additional factors and are therefore not predictable until the final device configuration is reached. Also, any configuration of the comparators that modifies their mode of operation (e.g., hysteresis on, clocked output mode, etc) can alter output states from initial settings until additional external conditions are reapplied to the device.
5
Specifications ISPPAC20
Timing Specifications (SPI Interface Mode)
TA = 25C; VS = +5.0V (Unless otherwise specified). SYMBOL PARAMETER CONDITION MIN. TYP. MAX. UNITS
Dynamic Performance trenc Minimum Rising Clock to ENSPI Time tfenc Minimum ESPI to Falling Clock Time tckmin Minimum Clock Period tckh TCK High Time tckl TCK Low Time tcss CS Setup Time tcsw Minimum CS Pulse Widths tdis TDI Setup Time tdih TDI Hold Time tdacs DAC Data Setup Time tdach tdozx tdov tdoxz DAC Data Hold Time TDO Float to Valid Delay TDO Valid Delay TDO Valid to Float Delay
10 10 100 50 50 35 40 15 10 15 10 60 60 60
ns ns ns ns ns ns ns ns ns ns ns ns ns
trenc
tfenc
trenc
tfenc
tcsw
ENSPI tckmin TCK tcss tckh tckl
CS tdacs DAC D0-D7 tdach
valid data
CS tdis tdih tcsminhi
TDI tdozx TDO tdov tdoxz
hi-z
hi-z
6
Specifications ISPPAC20
Pin Descriptions
Pin(s)
1,12,29 2 5 4 3 6, 7, 8, 9, 15, 16 10, 11, 13, 14 17, 25, 40 18 19 20 21 22 23 24 26 27, 28 30, 31 32 to 39 41, 42 43 44
Symbol
GND
Name
Ground
Description
Ground pins. All should normally be connected to same analog ground plane.
VREFout Common-Mode Reference Common-mode voltage reference output pin (+2.5V nominal). Must be bypassed to GND with a 1F capacitor. MSEL Multiplexer Control Multiplexer logic input pin. Selects either of two analog channels to one of the PACblock inputs. Input A selected when low, B when high. Internal pull-down to GND. ENSPI Enable SPI Mode Enable SPI logic input pin. When high, causes serial port to run in SPI mode. Internal pull-down to GND. TEST Factory Test pin Factory Test pin. Connect to GND for proper circuit operation. IN Inputs 1, 2, 3 (+ or -) Differential input pins, with two pins per input (e.g., IN2+ and IN2-). Plus or minus components of VIN, where differential VIN = VIN+ - VIN-. OUT Outputs 1,2 (+ or -) Differential output pins, with two pins per output (e.g., OUT2+ and OUT2-). Complementary with respect to VREFOUT, where differential VOUT = VOUT+ - VOUT-. VS Supply Voltage Analog supply voltage pins (5V nominal). Must all be connected together. Should all be bypassed to GND with 1F and .01F capacitors. TDI Test Data In Serial interface logic pin (input) for both JTAG and SPI operation modes. Input data valid on rising edge of TCK (JTAG). Internal pull-up to VS. TMS Test Mode Select Serial interface logic mode select pin (input). JTAG interface mode only. Internal pullup to VS. TCK Test Clock Serial interface logic clock pin (input). PC Polarity Control Polarity logic input pin. Controls polarity of one PACblock input. Operation determined by user configuration of device. Internal pull-down to GND. CS Chip Select Chip select logic input pin. SPI data and DAC parallel interface clock. Internal pull-up to VS. TDO Test Data Out Serial interface logic pin (output) for both JTAG and SPI operation modes. Output data valid on falling edge of TCK (JTAG). DMODE DAC Mode Select DAC mode logic input. When high, DAC can be loaded via the parallel interface pins D0-D7 using CS as the latch command. Internal pull-down to GND. WINDOW Window Comparator Out Window comparison logic pin (output). Configured by user to perform comparator logic functions. CPOUT Comparator Outputs Comparator logic pins (outputs). One pin for logic level of each comparator. CPIN Comparator Inputs Differential input pins, CPIN+ and CPIN-. Plus and minus components of VIN, where differential CPIN = CPIN+ - CPIN-. D0 to D7 DAC Data Inputs DAC data pins (inputs). Eight parallel inputs to DAC. Clocked by CS pin. D0 is the LSB and D7 is the MSB. DACOUT DAC Outputs (+ or -) Differential output pins (DOUT+ and DOUT-). Complementary with respect to VREFout, where differential DOUT = DOUT+ - DOUT-. CMVin Input for Optional VREFOUT Input pin for optional analog Common Mode Output Voltage (CMVin). Replaces VREFout (+2.5V) with this voltage for any user selected PACblock. CAL Auto-Calibrate Digital pin (input). Commands an auto-calibration sequence on a rising edge. Internal pull-down to GND.
6 IN3- IN3+ IN1- IN1+ OUT1- OUT1+ GND OUT2+ OUT2- IN2+ IN2- VS 7 8 9 10 11 12 13 14 WINDOW CP1OUT CP2OUT 15 16 17 TMS TDO TCK TDI PC CS DMODE 5 MSEL 4 ENSPI 3 TEST 2 VREFOUT 1 44 43 42 41 40 GND CAL CMVin DACOUT+ DACOUT- VS 39 38 37 36 35 D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) CPIN+ CPIN- GND
Connection Notes
1. All inputs and outputs are labeled with plus (+) and minus (-) signs. Polarity is labeled for reference and can be selected externally by reversing pin connections or internally under user programmable control. 2. All analog output pins are "hard-wired" to internal output devices and should be left open if not used. Outputs of uncommitted PACblocks are forced to VREFOUT (2.5V) and can be used as low impedance reference output buffers. VOUT+ and VOUT- should not be tied together as unnecessary power will be dissipated. 3. When the signal input is single-ended, the other half of the unused differential input must be connected to a DC common-mode reference (usually VREFOUT, 2.5V). 7
ISPPAC20
34 33 32 31 30 29
18 19 20 21 22 23 24 25 26 27 28
44-Pin PLCC
VS
Specifications ISPPAC20
Typical Performance Characteristics
Input Noise Spectrum
1000 Noise: Referred to Input G = 10
Noise Voltage (nV Hz)
CMR vs. Frequency
100 90 Common Mode Rejection (dB) 80 70 60 50 40 30
Power Supply Rejection (dB)
80 90
PSR vs. Frequency
70
100
60
50
40 30
10
1
10
100 1k 10k 100k 1M Frequency (Hz)
20
10
100
1k 10k 100k Frequency (Hz)
1M
100
1k
10k 100k Frequency (Hz)
1M
Small Signal BW vs. Gain
21 15 9 Gain vs. Frequency (dB) 3 -3 -9 -15 -21 -27 -33 -39 1k 10k 100k 1M Frequency (Hz) 10M
-100 -40
THD vs. Frequency (Gain=1)
-40
Rload = 300 = 5k = 1k = 600 = No Load
THD vs. Frequency (Gain=10)
Rload = 300 = 1k = 600 = 5k = No Load
G = 10 Total Harmonic Distortion (dB)
G=2 G=1
Total Harmonic Distortion (dB)
100k
G=5
-50
-50
-60
-60
-70
-70
-80 -90
-80 -90 -100
1k
10k Frequency (Hz)
1k
10k Frequency (Hz)
100k
Capacitive Load Handling
24 21
Percentage of Devices (%)
30 25
VOS Tempco
30
VREFOUT Tempco
3 Wafer Lots PDIP Pkg 0C to +85C
3 Wafer Lots PDIP Pkg -40C to +85C
Percentage of Devices (%)
25
18
Overshoot (%)
15 12 9 6 3 0
20
20
15
15
10
10
5 0
5 0
10
100 1k Capacitance (pF)
10k
-160
0 -80 +80 +160 Offset Tempco ( V/C)
-100
0 -50 +50 +100 Offset Tempco ( V/C)
8
Specifications ISPPAC20
Typical Performance Characteristics
10.34kHz Filter FC Accuracy
50 2000 Units PDIP Pkg
Percentage of Devices (%) Percentage of Devices (%)
46.46kHz Filter FC Accuracy
50 2000 Units PDIP Pkg
91.98kHz Filter FC Accuracy
50 2000 Units PDIP Pkg
30
30
Percentage of Devices (%)
-4 -3 -2 -1 0 1 2 3 4 Frequency Variation (%)
40
40
40
30
20
20
20
10
10
10
0
-4 -3
-2 -1 0 1 2 3 4 Frequency Variation (%)
0
0
-4 -3
-2 -1 0 1 2 3 4 Frequency Variation (%)
Large-Signal Response
Small-Signal Response
1.0V
Gain = 1 Load = No Load
1S
20mV
Gain = 1 Load = No Load
1S
Large-Signal Response with 600pF Load
Small-Signal Response with 600pF Load
1.0V
Gain = 1 Load = 600pF
1S
20mV
Gain = 1 Load = 600pF
1S
9
Specifications ISPPAC20
Theory of Operation Introduction
The ISPPAC20 includes two programmable analog macrocells called PACblocks, each emulating a collection of operational amplifiers, resistors and capacitors. Requiring no external components, it flexibly implements basic analog functions such as precision filtering, summing/ differencing, gain/attenuation and integration. Each PACblock contains a summing amplifier, two differential input instrument amplifiers, and an array of feedback capacitors. The capacitors, combined with a fixed value feedback element, provide more than 120 programmable poles between 10kHz to 100kHz with an absolute accuracy of 5.0 percent. Variable gain input instrument amplifiers make it possible to program any PACblock gain in integer steps between 1 and 10. More complex signal processing functions are performed by configuring both PACblocks in combination with each other to achieve a variety of circuit functions. The ISPPAC20 architecture is fully differential from input to output. This effectively doubles dynamic range versus single-ended I/O. It also affords improved performance with regard to specifications such as input common mode rejection (CMR) and total harmonic distortion (THD). Differential peak-peak voltage is determined by knowing the signal extremes on both differential input or output pins. For example, if V(+) equals 4V and V(-) equals 1V, the differential voltage is defined as V(+) - V(-) = Vdiff, or 4V - 1V = +3V. Since either polarity can exist on differential I/O pins, it is also possible for the opposite extreme to exist and would mean when V(+) equals 1V and V(-) equals 4V, the differential voltage is now 1V - 4V = -3V. To calculate the differential peak-peak voltage or full signal swing, the absolute difference between the two extreme Vdiff's is calculated. Using the previous examples would result in |(+3V) - (-3V)| = 6V. It can be immediately seen that true differential signals result in a doubling of usable dynamic range. For more explanation of this and other differential circuit benefits, please refer to application note AN6019. Input polarity is programmable without affecting input impedance or dynamic performance, since no internal change is made other than routing to the input amplifier. Single-ended operation is achieved by using either one input and/or one output pin, as required, and adjusting gain settings to achieve desired output levels. The ISPPAC20 operates on a single 5V supply and includes an internal reference generating 2.5V. This reference is made available externally through the voltage common-mode reference or VREFOUT pin (Pin 2). The output common mode voltage is always referenced to 2.5V, regardless of the input common mode level. It is possible, when desired, to use an externally supplied voltage instead of VREFOUT, however. This optional common-mode output voltage (VCM) must be provided by the user via the CMVIN input pin (Pin 43). The only limitation is this reference voltage must be between 1.25V and 3.25V. When an external voltage is present, an ISPPAC20 must be programmed, on a per-PACblock basis, to use the external reference instead of the internal 2.5V. Configuring an ISPPAC20 is accomplished using PAC-Designer, a Windows-based design environment. PAC-Designer includes an AC simulator for design verification prior to programming. The user can download the design to the ISPPAC20 at any time via the device's IEEE Standard 1149.1 (JTAG) compliant serial port directly from the parallel port of a PC using an ispDOWNLOADTM cable. Once downloaded, the circuit topology and component values are stored in non-volatile digital E2CMOS cells on the ISPPAC20 without any need for external programming voltages.
Architecture
In all ispPAC products, individual programmable circuit functions called PACellsTM are carefully combined to form larger analog macrocells or PACblocks. The ISPPAC20 has two such PACblocks that incorporate specially configured PACells to perform amplification, summation, integration and filtering. Each of the two filtering/summation or "FilSum" PACblocks within ISPPAC20 is comprised of three separate PACells, two input instrument amplifiers and an output summing amplifier (see Figure 1). The input amplifier PACells act as front-end gain stages for the FilSum PACblock and allow multiple signals to be summed together. The PACblock's output amplifier is similar to the familiar operational amplifier except that it has true differential outputs. Also included with each output amplifier is a filter capacitor array and switchable DC feedback path element. These components in combination enable the filtering and integrating functions of the FilSum PACblock.
10
Specifications ISPPAC20
Theory of Operation (Continued)
Figure 1. FilSum (Filtering/Summation) PACblock Diagram
IA1 gm1
VINVIN+
VIN+
CF
VIN
IAF gm3
VOUT+
functionality: Signals can be summed, the resistive amplifier feedback can be removed to create an integrator, the sign of PACblock transfer function can be changed without changing the input or output loading characteristics. The FilSum PACblock can precisely filter, amplify or attenuate signals, always maintaining the high impedance input qualities of instrumentation amplifiers.
IA2 gm2
VOUT
VOUT-
FilSum PACblock Operation
All ISPPAC20 inputs are differential, the input signal being the difference between input amplifier (IA) PACell pins VIN+ (Positive Input) and VIN- (Minus Input). The common mode value of the input is ignored, and as long as the inputs are not within one volt of the supply rails, the part is in its linear operating region. As the input signal range exceeds these limits, distortion begins to increase until clipping occurs. This is discussed further in the advanced topics section. The output is also differential, being the difference between output amplifier (OA) PACell pins VOUT+ and VOUT-. The output maintains high linearity to within 100mV of the supply rails under minimum load. The output has short circuit protection and is capable of driving resistive loads as low as 300 or capacitances as large as 1000pF. The output common mode voltage is maintained at VREFOUT independent of the input common mode level. That is, the output amplifier PACell "re-references" the common mode level of the input signal. This is accomplished by continuously sensing the output common mode voltage and comparing it to VREFOUT as shown in Figure 3, and makes it possible to use an individual FilSum PACblock as a VREFOUT reference as discussed in the section titled "Using VREFOUT". Figure 3. Output VREFOUT Re-Referencing
VIN
VIN-
CF
Each FilSum PACblock actually employs three instrument amplifier (IA) PACells: two at the input (IA1 and IA2) and one as a feedback element around the op amp (IAF). The instrument amplifier PACells all have differential I/O and convert an input voltage to an output current (refer to Figure 2). This type of amplifier is sometimes referred to as an operational transconductance amplifier or OTA. When a differential input voltage is applied to these IAs, it is converted to a current proportional to the input signal. Because an AC signal common to both of the high impedance inputs of the IA does not create a net difference in the input signal, it is rejected by the amplifier. This characterizes the function of what is commonly known as an instrument amplifier and is a very desirable property because it acts to preserve the integrity of small signals in the presence of otherwise overwhelming noise. Figure 2. Instrument Amplifier PACell
VIN+ VIN VINgm
IM IP
CF
IAF
VOUT
The two input instrument amplifiers have a programmable transconductance (gm) value in 10 steps between 2A/V and 20A/V with programmable input polarity, whereas the feedback amplifier is fixed at 2A/V. The IA PACells exhibit extremely high input impedance so they don't load circuitry driving them and their outputs can be enabled or disabled under E2CMOS control, effectively switching them in and out of the FilSum PACblock circuitry. These simple characteristics permit a great deal of
CF
VCMIN (2.5V)
Input Offset Auto-Calibration. A unique feature of the ISPPAC20 is its ability to automatically calibrate itself to achieve very low offset error. This is done utilizing onchip circuitry to perform an auto-calibration (auto-cal)
11
Specifications ISPPAC20
Theory of Operation (Continued)
sequence every time the device is turned on, or anytime it is commanded externally via the CAL pin or by a JTAG programming command. With this feature, the degradation of device offset performance that could occur over time and temperature is dramatically reduced. Specifically, this means one PACblock of an ISPPAC20 in a gain configuration of one is guaranteed to never have an input offset error greater than 1mV, after being auto-calibrated. For higher gain settings when offset is especially important, the error is not multiplied by gain, but is instead divided by it, due to the unique architecture of the ISPPAC20. When an individual PACblock is configured in a gain of ten, that results in an input referred offset error that never exceeds 100V. Internally, auto-calibration is accomplished by simultaneous successive approximation routines (SAR) to determine the amount of offset error referred to each of the two PACblock output amplifiers of the ISPPAC20. That error is then nulled by a calibration DAC for each output amplifier. The calibration constant is not stored in E2CMOS memory, but is recomputed each time the device is powered up or auto-cal is otherwise initiated. Initiation of auto-cal occurs when an ISPPAC20 is powered on as part of its normal power on routine, or by a positive going pulse to the CAL pin (Pin 44), or by issuing the appropriate JTAG command. During auto-cal, all ISPPAC20 OA PACell outputs are driven to 0V and remain there until calibration is complete. The timing for the calibration process is generated internally. At power on, the sequence takes a maximum of 250ms, and when auto-cal is initiated via the CAL pin or by JTAG programming, it takes a maximum of 100ms to complete. The longer time required at power on insures the device power supply reaches its final value before calibration begins. Additional attempts to initiate auto-cal once calibration is in progress are ignored. Finally, the only direct indication of auto-cal completion will be the device's OA outputs returning to operational values from the 0V clamped state. To insure maximum accuracy of the auto-cal procedure, all digital signals to the ISPPAC20 should be suspended when calibration is in progress to avoid feed-through of noise to critical analog circuitry. This is especially true when auto-cal is initiated via JTAG command and the programming port is in use. There is sufficient time, however, to clock the JTAG controller back to its "reset" state without affecting the calibration process. feedback capacitance to optimize the step response. The trimmed step response resembles that of a critically damped system with minimum overshoot. The bandwidth trim ensures a nominal feedback capacitance is always present, limiting the small signal bandwidth of an OA PACell to about 600kHz when configured in a gain of 1 (G=1). This should not be confused with the gain-bandwidth product of the op amp within the output amplifier PACells which is approximately 5MHz. It is important to note that the individual output amplifiers are always in essentially the same fixed gain configuration and do not, therefore, contribute to a decrease in signal bandwidth at higher PACblock gain settings. Since the gain of an individual PACblock is determined by varying the gm of the input amplifier, bandwidth is not reduced in direct proportion to gain, as it would be in a traditional voltage feedback amplifier configuration. Specifically, small signal bandwidth is only reduced by a factor of 2, not the expected 10, with a PACblock gain setting change of G=1 to G=10. This is a significant advantage of the PACblock architecture.
Pole Accuracy Trim. Separate from the bandwidth trim capacitance, each FilSum PACblock contains a range of user selectable op amp feedback capacitance. This is made possible by a parallel arrangement of seven capacitors, each in series with an E2CMOS switch. The user controls the position of the switches when selecting from the available capacitor values. The resulting capacitance is in parallel with the op amp feedback element, IAF, making 128 possible pole locations available. The capacitor values are not binarily weighted, instead they are chosen to optimize and concentrate pole spacing below 100kHz. There are 122 poles between 10kHz and 96kHz, which guarantees a step of no greater than 3.2% anywhere in that frequency range (to the nearest computed pole location). In fact, step size in over 50% of that range is less than 1.0%. Finally, capacitors are trimmed to achieve 5.0% accuracy (absolute) with regard to their nominal value.
PACblock Transfer Function
The block diagram for a PACblock is shown in Figure 1. The transfer function for a transconductor is:
IP = - gm * VIN IM = gm * VIN
(1) (2)
Bandwidth Trim. The bandwidth of an OA PACell is trimmed during manufacturing by adjusting the amplifier's
Using KCL (Kirchoff's current law) at the op amp inputs and assuming the input is connected to IA1 only:
12
Specifications ISPPAC20
Theory of Operation (Continued)
- VIN gm1 + VOUT gm3 + ( VOUT + - ( V - ))sCF
VIN gm1 - VOUT gm3 + ( VOUT - - ( V +))sC F
(3a) (3b)
Figure 4. PAC-Designer FilSum PACblock
PACblock 2 k1 IA1 Summation IA2 k2 kN =-1, 2...10 OA1 RF 2 Feedback Enable CF 1pF to 62pF Differential Output
where V- and V+ are the voltages at the op amp inverting and non-inverting inputs respectively. Because of feedback they are equal, so
Two Differential 2 Inputs
- VIN gm1 + VOUT gm3 + ( VOUT + sCF ) = VIN gm1 - VOUT gm3 + ( VOUT - sCF )
(4)
2.5V CommonMode Voltage Input
and the differential output voltage VOUT is the difference VOUT+ - VOUT- ,
VOUT = VIN gm1 sCF gm3 + 2
The FilSum PACblock implements two primary functions: the lossy integrator (low pass filter) and the integrator, both with gain.
(5a)
Lossy Integrator. The lossy integrator's schematic within PAC-Designer is shown in Figure 5. Manipulating the PACblock transfer function of Equation 5 to better show the pole frequency yields:
k V +k V VOUT = - 1 IN1 2 IN2 sCF 1+ 2gm
Since the PACblock has two separate inputs (IA1 and IA2) summed at the output amplifier input:
VOUT k g V + k 2 gm VIN2 = 1 m IN1 sCF gm3 + 2
(6)
(5b)
Figure 5. PAC-Designer PACblock Lossy Integrator
CF
The input amplifiers have a programmable gain of k*2/V (gm1 and gm2) where k is an integer from -10 to 10. The feedback amplifier transconductance gm3 is fixed at 2/V, but may be disabled (gm3 = 0) to open-circuit the output amplifier's resistive feedback. The programmable feedback capacitance lies in the range 1pF to 62pF. The PACblock model from PAC-Designer is shown in Figure 4. The output amplifier is configured as an inverting mode op amp and illustrates the summing configuration. The input instrument amplifiers are shown to make it clear that unlike a typical inverting op amp, the PACblock input impedance is extremely high. The input amplifier (IA) transconductance (gain) is shown as the value (k) above or below each amplifier. The gain of IA1 and IA2 are independently programmable. Because the feedback transconductor IAF (designated here as RF) can be disabled by the user, a user configurable switch is shown in series.
k1 VIN1 IA1
RF VIN2 OA1 IA2 k2 2.5V VOUT
The DC gain of each input is set by k1 or k2 respectively, the gain constant for the input amplifiers. Below the pole frequency, this circuit can be viewed as a gain block. Because of the bandwidth trim capacitance, there is a minimum value of CF causing the bandwidth to be approximately 550kHz when the DC gain is one. For larger gains, the input amplifier bandwidth begins to dominate the overall PACblock response, limiting the bandwidth to about 330kHz when the gain is 10. Examining this transfer function shows the pole frequency is (1/2)(2gm/C). Since gm = 2/V and 1pF CF 62pF, then 600kHz fP 10kHz. Due to the selection options for feedback capacitance, there are at least 120 poles between 10kHz and 100kHz.
13
Specifications ISPPAC20
Theory of Operation (Continued)
Integrator. Switching out RF (turning off IAF) removes the feedback element as shown in Figure 6. The integrator's transfer function can be derived from Equation 5b by setting gm3 = 0 (open circuit IAF (RF)).
Figure 6. PAC-Designer PACblock Integrator (IAF Disabled; gm3 = 0)
k1 VIN1 IA1 RF VIN2 OA1 IA2 k2 2.5V VOUT
IN3 -1 IA3 OA2 2.5V PACblock 2
Figure 7b. Biquad Bandpass Filter Schematic
OUT1
MSEL = A
15.08 pF IN1 a -1 IA1 PACblock 1
CF
b IN2 IA2 2.5V 1 30.15 pF OA1
k V +k V VOUT = - 1 IN1 2 IN2 sCF 2gm
3V
IA4 -1
SRE=on
(7)
1.5V OUT2
Polarity Control: PC pin
The integrator slope is proportional to 1/f and, for the case of a single input, the transfer function magnitude equals |k| when the frequency is (1/2)(2gm/C). The integrator should not be used as a stand-alone circuit element. It needs to be used in configurations that provide DC feedback to ensure the output does not saturate, as illustrated by the biquad filter circuit below.
PC = 0
Application Examples
Biquad Filter. By simply combining the two structures, the integrator providing feedback around the lossy integrator, creates a useful circuit. The block diagram is shown in Figure 7a and the schematic from PAC-Designer is shown in Figure 7b.
Figure 7a. Biquad Bandpass Filter Block Diagram
Error B s 1+ p 1 VOUT1 (OUT1)
The transfer function OUT1(s)/IN1(s) is a band pass filter with programmable gain, Q and center frequency. Note the presence of DC feedback around the integrator. It can also be seen that the transfer function VFB(s)/VIN(s) implements a lowpass filter. This application is discussed further in a separate application note.
Attenuator. The PACblock architecture makes variations possible on these two basic building blocks just described. An example uses summation to connect an input amplifier (IA2) in parallel with the feedback element (RF), as shown in Figure 8.
Figure 8. PACblock AV < 1
k1 VIN1 IA1 RF OA1 2.5V k2 VOUT CF
VIN (IN1)
VOUT2 (OUT2)
VFB
A s
IA2
14
Specifications ISPPAC20
Theory of Operation (Continued)
The result is a circuit whose transfer function is:
VOUT =VIN k1 k2 + 1+ sCF 2gm
(8)
directly connected. An example is shifting the DC level of a signal connected to the input of a PACblock. In this case, the signal is AC coupled and "terminated" in VREFOUT through a minimum total resistance of 100k. Referring to Figure 10b, if RIN is greater than 200k then the VREFOUT pin may be used without buffering.
The gains k1 and k2 are independently set by the user; this circuit can either amplify or attenuate an input signal. The one in the denominator is due to RF; if RF is disabled, this term is eliminated. The level of attainable attenuation is as low as 1/11 (-20.8dB) with R F enabled or 1/10 (-20dB) with RF disabled. When configuring a PACblock to attenuate, it is necessary to increase the value of feedback capacitance to maintain stability. Increasing feedback capacitance has the same beneficial effect as for a discrete op amp: It increases the network's phase margin which assists in maintaining stability.
Interfacing
When used in a single-supply system where the system common mode voltage is near VS/2, signals may be directly connected to the ISPPAC20 input. If the input signal does not have such a DC bias, then one needs to be added to the signal in order to accommodate the input requirements for the ISPPAC20. A DC coupled bias can be added to a signal by using a voltage divider circuit as shown for one-half of the differential input in Figure 10a. Normally the choice for the reference DC voltage is the supply voltage, but other values may be used if necessary (and available). Figure 10a. DC Biasing an Input Signal
Using VREFOUT
The VREFOUT output is high impedance and it should be buffered when used as a reference. A PACblock can be made into a VREFOUT buffer as shown in Figure 9. The PACblock inputs are left unconnected and the feedback closed. In this condition the input amplifiers are tied to VREFOUT and the output amplifier's outputs are thus forced to VREFOUT or 2.5V. Either output is now a VREFOUT voltage source. This reference has the same drive capabilities of any ISPPAC20 output. However, do not short the two outputs together. There is a small potential difference between them which will cause a steady state current to flow, thus needlessly dissipating power. Figure 9. PACblock as VREFOUT Buffer
OUT1=2.5V Unconnected 1.07pF
VREFOUT
VIN+ VSE VIN*
*Single-Ended V SE: Connect to VREF OUT or other DC Reference. *Differential V SE: Duplicate Vin+ Network on Vin-.
OUT1
1 IA1
PACblock 1
V R VREFOUT R1 VIN+ = SE 2 + R1 + R 2 R1 + R 2
IN1
IA2 -1
OA1 2.5V
It is not always necessary to buffer the VREFOUT output. If it is used to reference a high impedance source, i.e., one that does not require more than 10A, then it can be
Where DC coupling is not required, the input signal may be AC coupled as shown in Figure 10b. This circuit forms a high pass filter with a cutoff frequency of 1/(2RC) and adds the necessary DC bias to the signal to accommodate the ISPPAC20 input requirements. The DC reference should equal VS/2, making VREFOUT the natural choice. The minimum resistance when using the VREFOUT buffer circuit of Figure 9 is 600; when using the VREFOUT output pin it is 200k (as discussed earlier).
15
Specifications ISPPAC20
Theory of Operation (Continued)
Figure 10b. AC-coupled Input with DC Bias swing is reduced. The output is capable of 10mA, so any DC current raises the minimum allowable load impedance.
Noise vs. Gain
CIN VIN+ CIN VINRIN
Noise gain is the gain of a circuit configuration to its combined input-referred circuit noise. The noise gain of an inverting op amp circuit is:
Noise Gain = 1+ Closed Loop Voltage Gain
(9)
In this case, the noise gain of the circuit increases proportionally to the circuit gain. A FilSum PACblock contains an input amplifier stage followed by an output amplifier. In this way it can be viewed as a system, with each of the components having its own contribution to the overall noise as shown in Figure 11. Both the output amplifier noise (N2) and input amplifier noise (N1) contribute to the overall noise performance, but the contribution due to the output amplifier dominates except at input gains near 10. The result is that the SNR of a FilSum PACblock is nearly constant versus gain. This is different than the behavior predicted by Equation 9. Figure 11. Multistage ispPAC Noise Diagram
VREFOUT
Single-ended Operation
Single-ended signals may be connected to the ISPPAC20 input and one of the two differential ISPPAC20 outputs can be used to drive single-ended circuitry. So, in addition to fully differential I/O, either the input, output or both may be used single-ended.
Single-ended Input. To connect the ISPPAC20 differential input to a single-ended signal, one of the differential inputs needs to be connected to a DC bias, preferably VREFOUT. The input signal must either be AC coupled (as in Figure 10b) or have a DC bias equal to the DC level of the other input. Since the input voltage is defined as VIN+- VIN-, the common mode level is ignored. The signal information is only present on one input, the other being connected to a voltage reference. Single-ended Output. Connecting the output to a singleended circuit is simpler still. Simply connect one-half of the differential output, but not the other. Either output conveys the signal information, just at half the magnitude of the differential output. The DC level of the singleended output will be VREFOUT due to the re-referencing aspect of the FilSum PACblock. If the load is not AC coupled and is at a DC potential other than VREFOUT, the load draws a constant current. Using one of the differential outputs halves the available output voltage swing (3VPP versus 6VPP) and since the output current capacity is the same whether driving differentially or single-ended, a single output can drive twice the load as the differential output (150 vs. 300 or 2000pF vs. 1000pF). If the load requires DC current, the amount available for voltage
N1
G1
N2
G2
Stage One
Stage Two G2 = Constant
2
Output Noise Voltage = G1 G2
2 N1 +
N2 G1
(10a)
If N2/G1 > 3*N1, then
Output Noise Voltage G2N2
(10b)
There is a few dB decrease in SNR as the gain approaches 10. This characteristic implies the input amplifier noise contribution is approaching that of the op amp. As the gain of the input amplifier nears 10, its noise contribution in Equation 10a (N1) approaches that of the op amp and becomes a factor in the overall output noise voltage, causing it to increase.
16
Specifications ISPPAC20
Theory of Operation (Continued) Input Common-Mode Voltage Range
For the ISPPAC20, both maximum input signal range and corresponding common-mode voltage range are a function of the input gain setting. The maximum input voltage times the gain of an individual PACblock cannot exceed the output range of that block or clipping will occur. The maximum guaranteed input range is 1V to 4V, with an extended typical range of 0.7V to 4.3V for a 5V supply voltage. The input common-mode voltage is VCM = (VCM+ + VCM-)/2. When the value of VCM is 2.5V, there are no further input restrictions other than the previously mentioned clipping consideration. This is easily achieved when the input signal is true differential and referenced to 2.5V. When VCM is not 2.5V and the gain setting is greater than one, distortion will occur when the maximum input limit is reached for a particular gain. The lowest VCM for a given gain setting is expressed by the formula, VCM- = 0.675V + 0.584G*VIN where G is the gain setting and VIN is the peak input voltage, expressed as |VIN+ - VIN-| and the highest VCM is VCM+ = 5.0V - VCM- where 5V is the nominal supply voltage. In Table 1, the maximum VIN for a given VCM- to VCM+ range is given. If the maximum VIN is known, find the equivalent or greater value under the appropriate gain column and the widest range for VCM will be found horizontally across in the left-most two columns. Only a VCM range equal to or less than this will give distortionfree performance. Conversely, if the maximum VCM range is known, the largest acceptable peak value of VIN can be found in the corresponding gain column. All values of VIN less than this will give full rated performance.
Table 1. Input Common-Mode Voltage Range Limitations
Input Voltage Magnitude (Volts-Peak) VCM1.000 1.100 1.200 1.300 1.400 1.500 1.600 1.700 1.800 1.900 2.000 2.100 2.200 2.300 2.400 2.426 2.500 VCM+ 4.000 3.900 3.800 3.700 3.600 3.500 3.400 3.300 3.200 3.100 3.000 2.900 2.800 2.700 2.600 2.574 2.500 G=1 0.557 0.728 0.899 1.071 1.242 1.413 1.584 1.756 1.927 2.098 2.270 2.441 2.612 2.783 2.955 3.000* 3.126 G=2 0.278 0.364 0.450 0.535 0.621 0.707 0.792 0.878 0.964 1.049 1.135 1.220 1.306 1.392 1.477 1.500* 1.563 G=3 0.186 0.243 0.300 0.357 0.414 0.471 0.528 0.585 0.642 0.699 0.757 0.814 0.871 0.928 0.985 1.000* 1.042 G=4 0.139 0.182 0.225 0.268 0.310 0.353 0.396 0.439 0.482 0.525 0.567 0.610 0.653 0.696 0.739 0.750* 0.782 G=5 0.111 0.146 0.180 0.214 0.248 0.283 0.317 0.351 0.385 0.420 0.454 0.488 0.522 0.557 0.591 0.600* 0.625 G=6 0.093 0.121 0.150 0.178 0.207 0.236 0.264 0.293 0.321 0.350 0.378 0.407 0.435 0.464 0.492 0.500* 0.521 G=7 0.080 0.104 0.128 0.153 0.177 0.202 0.226 0.251 0.275 0.300 0.324 0.349 0.373 0.398 0.422 0.429* 0.447 G=8 0.070 0.091 0.112 0.134 0.155 0.177 0.198 0.219 0.241 0.262 0.284 0.305 0.327 0.348 0.369 0.375* 0.391 G=9 0.062 0.081 0.100 0.119 0.138 0.157 0.176 0.195 0.214 0.233 0.252 0.271 0.290 0.309 0.328 0.333* 0.347 G=10 0.056 0.073 0.090 0.107 0.124 0.141 0.158 0.176 0.193 0.210 0.227 0.244 0.261 0.278 0.295 0.300* 0.313
*Peak input voltage for guaranteed performance at a given gain setting.
17
Specifications ISPPAC20
Theory of Operation (Continued) DAC PACell
The ISPPAC20 contains an 8-bit, voltage output, digitalto-analog converter (DAC) PACell with many unique features and options. Interface modes are user selectable and include a direct 8-bit parallel port, a serial JTAG address mode, or serial SPI address mode. The output of the DAC is fully differential, making it compatible with the rest of the ISPPAC20's internal analog I/O. The DAC's voltage output is available via external pins as well as by on-chip routing for optional internal connection to either the comparator PACells or any of the instrument amplifier input PACells. The choice of addressing modes depends largely on application needs, but the primary benefit of each addressing mode is as follows:
JTAG/E2: Power-up state of DAC is determined by E2 configuration memory. The DAC input code can still be changed, but only by reprogramming the E2 memory via JTAG command and subject to the maximum number of programming cycles allowed. This is the preferred mode to use when the DAC setting must be retained when device power has been cycled off and then on again. Parallel: This mode allows direct parallel update access to the DAC. The DAC can be updated continuously without affecting E2 programming cycle endurance issues. The DAC E2 configuration cells can still be programmed via serial JTAG commands directly from the value stored in the parallel input data latches at any time, if desired. JTAG/Direct: The DAC can be addressed directly, bypassing the E2 configuration memory via the standard JTAG serial interface protocol. Using this serial addressing mode retains the ability to reprogram the ISPPAC20 DAC at any time without having to reconfigure the interface from one mode to another. SPI: The DAC can be addressed directly, bypassing the E2 configuration memory via an SPI compatible serial interface protocol. The SPI serial interface is one of the most widely used protocols for communication with mixed signal devices of all types. While in the SPI addressing mode, programming of the DAC E2 configuration memory is not possible.
DAC Data Input Coding
Data input to the DAC, whether in serial or parallel mode, determines its output value. The coding of the DAC is in straight binary and corresponds to input to output relationship shown in Table 2, DAC I/O. In all serial modes, 8 bits of data are clocked in with D0 (the LSB) being first in the data stream and D7 (the MSB) being last.
DAC Address Modes
Addressing modes are controlled from within PAC-Designer by one user-programmable E2 bit (DSthru) and by two external pins (DMode and ENSPI). Figure 12 diagrams the various input data paths used to implement the various ISPPAC20 DAC addressing modes. Also included in the figure is a truth table of the user E2 settings and input logic levels required to enable them. All serial data input modes are 8 bits long and clocked in LSB (D0) first. Table 2. DAC I/O
DEC 0 32 64 96 127 128 129 160 192 224 255 Code HEX 00 20 40 60 7F 80 81 A0 C0 E0 FF
-Full Scale (-FS)
MS - 1LSB Mid Scale (MS) MS + 1LSB
+Full Scale (+FS) LSB Step Size +FS + 1LSB
Nominal Voltage Vout+ (V) Vout- (V) 1.0000 4.0000 1.3750 3.6250 1.7500 3.2500 2.1250 2.8750 2.4883 2.5117 2.5000 2.5000 2.5117 2.4883 2.8750 2.1250 3.2500 1.7500 3.6250 1.3750 3.9883 1.0117 x + 0.0117 x - 0.0117 4.0000 1.0000
Vout (Vdiff) -3.0000 -2.2500 -1.5000 -0.7500 -0.0234 0.0000 0.0234 0.7500 1.5000 2.2500 2.9766 0.0234 3.0000
18
Specifications ISPPAC20
Theory of Operation (Continued)
Figure 12. ISPPAC20 DAC Interface Options
CS Serial Input Data Latches (pre-set to 80h at power-up) (4) TDI TCK
3:1 MUX
JTAG/Direct & SPI TDO
Serial DAC Input Shift Register (SR) (3) (2) DAC Address E2 CMOS Memory (1) JTAG/E2
DAC Inputs
Address Mode Logic
Parallel CS(5) Parallel Input Data Latches (pre-set to 80h at power-up)
ENSPI Input Pin DSthru E2 Bit DMode Input Pin
DAC Parallel Input Data Pins D0-D7
Registers updated after JTAG command(s): (1) DBE, PrgDAC (DMode=1) (2) AddDAC, DBE, PrgDAC (DMode=0) (3) VerDAC (4) AddDAC (E2 bit DSthru=1, ENSPI=0) SPI mode only: Rising edge of CS (5) Rising edge of CS (only if DMode=1)
ENSPI DSthru DMode Address Pin E2 Bit Pin Mode 0 0 0 JTAG/E2 1 0 0 Parallel X 1 0 JTAG/Direct X X 1 SPI
Table 3. DAC Address Modes
Action E2 Cells Programmed Via: DAC Input Comes From: DAC Updated On: Rising Edge CS Updates: DAC Output at Power-Up: TDO Serial Output in Hi-Z State During JTAG AddDAC Operation JTAG/E2 Serial Mode Serial Input SR E2CMOS Memory During Update-DR, falling edge TCK (1) Serial Latch Stored E2 Value Parallel Mode Parallel Latches Parallel Latches Rising Edge CS Serial Latch Parallel Latch JTAG/Direct Serial Mode Serial Input SR Serial Latch During Update-DR, falling edge TCK Serial Latch SPI Serial Mode No E2 Access Serial Latch Rising Edge CS Serial Latch
80h (Vout+, Vout-=2.5V) 80h (Vout+, Vout-=2.5V) 80h (Vout+, Vout-=2.5V) No TDO if TCK pin is not clocked If E2 bit DisTDO =1, Otherwise active during Shift-DR/IR JTAG state When CS is high
If E2 bit DisTDO =1, Otherwise active during Shift-DR/IR JTAG state
Notes: (1) DAC output goes from -FS to +FS during E2 programming cycle (JTAG DBE or DAC Bulk Erase, and PrgDAC or Program DAC commands) before settling to the final input code value.
19
Specifications ISPPAC20
Theory of Operation (Continued) DAC Address Mode Details
DAC Parallel Mode Addressing. The parallel addressing mode uses the eight external (D0-D7) data pins of the ISPPAC20 to address the DAC. The DMode (DAC E2/parallel Mode) logic input pin determines whether the input data path is routed from E2 memory (DMode =0) or directly from the parallel input data pins (DMode =1). In addition, both serial input modes (JTAG/Direct and SPI) must be disabled to access the parallel input mode. This means the E2 bit DSthru (Direct Serial Throughput) is selected to be 0, the ENSPI (Enable SPI serial mode) logic input pin is low and the DMode logic input pin is high. Data is latched into the parallel data latches on a positive going edge of CS (Chip Select) and the output of the DAC changes to its new value at this time according to the setup timing constraints in the AC specification waveform tables. When a device is first turned on, the parallel data latches are initialized to code 80h, which corresponds to 2.5V on both DAC analog output pins. To otherwise start up with the value DAC code programmed in E2 memory (instead of the default 80h), the DMode logic input pin must remain low until the first data update of the parallel input data latch at which time the contents of the DAC reflect the parallel data input pins. JTAG/E2 Serial Mode Addressing. The JTAG/E2 serial mode is the only addressing mode where the ISPPAC20 powers up with the DAC set to the input code stored in its internal E2 configuration memory. In all other modes the DAC defaults to input code 80h (2.5V on both output pins) at turn on. The DAC can be changed while in this mode, but only by a process of reprogramming the DAC E2 memory cells themselves via routine JTAG commands. This is sometimes desirable when a particular DAC output operating point is reached that the system is then required to "remember". This update can be accomplished via programming the DAC directly through the JTAG interface of the ISPPAC20 without perturbing any of the rest of the chip's function or operation.
It should be noted, however, that the DAC outputs are directly determined by the state of their E2 configuration memory. That means if the DAC E2 cells are reprogrammed to change codes, the DAC output will follow the E2 transition states until their final programmed value is reached. A DAC E2 programming cycle consists of an erase during which the output goes to minus full-scale (-FS), then a write during which the output briefly goes to plus full-scale (+FS) before the E2 cells transition to their final programmed values and the output settles there as well. This phenomenon only applies when in the JTAG/ E2 serial address mode. In all other addressing modes, the DAC changes to its new value immediately after a latch register is clocked.
JTAG/Direct Serial Mode Addressing. Unlike the previous method of addressing the ISPPAC20 DAC from the E2 cells directly, JTAG/Direct serial mode interfaces the DAC via the serial input data latches. After a data word is shifted into the serial input shift register via JTAG command (AddDAC), the DAC is immediately updated on the falling edge of clock TCK in the UpdateDR state. The E2 cells are bypassed entirely in this mode. The advantages are that the DAC can be addressed separately from the rest of the ISPPAC20 via the serial JTAG interface and can be continuously updated an unlimited number of times. The serial data rate of 5MHz is much faster than the settling time of the DAC making this an acceptable way of addressing and changing the output for full speed AC applications. It is, of course, also suitable for applications where the DAC output needs to be varied from time to time, and the need to store the last code before power down on-chip is not critical.
Like all other addressing modes except JTAG/E2, the JTAG/Direct serial mode powers up with the DAC input code set to 80h, which results in both analog DAC outputs being at 2.5V. If desired, the DAC may be loaded with the code previously stored in the DAC E2 memory by issuing a VerDAC JTAG command and then transitioning through the UpdateDR state from within an AddDAC JTAG command. JTAG/Direct Serial Mode is selected by setting the DSthru E2 bit to 1 as part of the initial device configuration programming process, either during design using the PAC-Designer software, or on the printed circuit board via embedded or local programming, or by some other pre-programmed manufacturing delivery process.
SPI Serial Mode Addressing. Finally, the ISPPAC20 can be addressed using a serial interface mode that is compatible with the industry standard SPI protocol (serial peripheral interface, a Motorola trademark). Like the JTAG/Direct serial mode, the DAC E2 configuration is bypassed in SPI serial mode allowing the DAC to be updated continuously and for an unlimited number of cycles if desired. Whenever the ENSPI (enable SPI) pin is high, the ISPPAC20 is in the SPI serial addressing mode and the 8 bits of DAC input data can be clocked in if the device is selected by the CS (chip select) pin being low. The data is latched in and the DAC output changes on a subsequent rising edge of CS.
20
Specifications ISPPAC20
Theory of Operation (Continued) Comparator PACell Operation
The ISPPAC20 has two programmable, double difference comparator PACells on chip that include many user programmable options to optimize their utility. These comparators operate no differently than any standard comparator, that is whenever the +(plus) input is positive with respect to the -(minus) input, its logic output will be high, otherwise they will be low. Unlike most other available comparators, however, inputs to the ISPPAC20 comparator PACells are fully differential (true doubledifference comparators). Both the plus and minus inputs of the ISPPAC20 comparators have a Vin+ and a Vin- with the differential input voltage defined as [(Vin+) - (Vin-)]. This means the comparator output is high whenever the differential voltage on the +(plus) input is positive with respect to the differential input voltage on the -(minus) input. It should be noted that the plus input path of CP2 effectively performs a negation of the differential voltage to that input (denoted by an additional inversion symbol in PAC-Designer). The utility of this operation is that an identical differential signal can be applied to the plus inputs of both comparator PACells and result in a symmetrical window about 2.5V. For example if the +1.5VDC input line is connected to both comparator plus inputs, CP1's plus input is +1.5V differential, and CP2's plus input is then -1.5V differential. If both minus inputs were both connected to CPin in PAC-Designer (the external comparator input pin), the result would be a logic 1 on CP1 when the external input was below +1.5Vdiff and a logic 1 on CP2 whenever it was above -1.5Vdiff. Furthermore, the WINDOW (window compare output pin) which is the exclusive OR of the two CPout pins would result in a logic 0 any time the signal was between +-1.5Vdiff on the external input and a logic 1 anytime it was outside that window.
Comparator Input Options
All inputs to the comparators can be accessed from several different points including signals external to the ISPPAC20. When first shown in the PAC-Designer software design entry screen, the inputs to the comparators appear not to be connected to any signal source. In fact, whenever no connection is indicated, the Vin+ and Vinlines (denoted by a single line in PAC-Designer) are both connected to 2.5V DC. That means that if the minus input were left unconnected in PAC-Designer, the differential voltage on that input would be 0V (2.5V - 2.5V = 0V). At this point any positive differential voltage on the plus input of that comparator would result in a logic 1 output, and any negative a logic 0. The output of PACblock 2 (OA2) is available to any input of CP1 or CP2 as is the external input pin, IN3. In the case of a signal on IN3, it could be routed to one of the PACblocks as well as the comparators to control a switching threshold or other level determined event. Using IN3 as a standalone input going only to one of the comparators and the CPIN pin (comparator external input), both the plus and minus inputs to the comparators could come from entirely external signals. The most common source for deriving reference levels on the comparators would be directly from the internal 8-bit DAC. In addition to the 256 voltage levels being directly available from the DAC, a constant 1.5V and 3.0V is also available for setting a comparator input threshold. These fixed values free the DAC to be used for other circuit purposes such as nulling system offset voltages or programming ADC reference inputs.
Optional Comparator Hysteresis
Another programming option provided for the user is the ability to enable or disable comparator hysteresis. Hysteresis is useful in situations where a slow moving signal, or an uncertain transition condition exists that would otherwise result in excessive noise on the comparator output. The magnitude of this hysteresis is nominally 47mV and can be either enabled or disabled in E2 configuration memory and concurrently affects both comparators. It is symmetrical with respect to any input change, which means that regardless of which direction the input causing the state change comes from (with respect to the reference input), it will have to change at least 47mV above or below the reference to cause another output state change. The default initial condition of the hysteresis setting is on. Comparator hysteresis can be disabled by selecting the appropriate edit symbol command in PAC-Designer and making the change.
Polarity Control of IA4
Normally the gain and polarity for an individual IA (instrument amplifier input) PACell is chosen from the range of choices from -10 to +10 (in integer steps) directly in PACDesigner from a single gain setting listbox choice. With the ISPPAC20 this is the case for IA1, IA2 and IA3. IA4 on the other hand, only has gain choices from -10 to -1 available in this particular dialog box. The reason is the positive gains are actually realized by internally reversing the polarity of the differential inputs, effectively multiplying the ten negative gains by -1 to achieve the positive gain values. With IA4, the control of this inversion
21
Specifications ISPPAC20
Theory of Operation (Continued)
Table 4. Comparator Logic Control Modes/Options
Mode Fixed, Non-Inverting PC Pin Function None (internal). Description Always generates a +1 times whatever the gain setting of IA4 is. IA4 can be set to gains of -1 to -10 in this mode. Display of the gain setting for IA4 in PAC-Designer is of the correct polarity. IA4 gain setting is correct as shown in PAC-Designer (-1 to -10) if PC pin input equals a logic 1 (no inversion). If the PC pin input equals a logic 0, the setting of IA4 will be inverted with respect to what is displayed in PAC-Designer. Terminating the PC pin low (externally) in this mode is the most direct way of achieving a constant setting of positive gain (+1 to +10) for IA4. Both comparators combine to generate a set/reset function on the WINDOW logic output pin instead of the usual XOR function. This signal is also routed internally to IA4 for polarity control. When PC is a logic 0, CP1 positive transitions generate a set command and positive transitions of CP2 a reset command. For example, if PACblock 2 is configured as an integrator and its output is fed to CP1 and CP2 (configured for window comparison), a voltage controlled oscillator will result from the RS Flip-Flop set/reset reversing the polarity every time the integration exceeds the upper and then lower window boundaries in sequence. When PC is a logic 1, the output of OA2 goes immediately to 2.5V and stays in "hold" mode until PC returns to a logic 0. This effectively implements a gated oscillator function. In this mode, the output of comparator 1 (CP1) controls the polarity of IA4, a logic 1 = no inversion, a logic 0 = inverted. When the output of CP1 is in the direct mode, the polarity control is all internal. If the CP1 Buffer E2 bit is set, CP1 changes can only occur if clocked by the PC pin externally (rising edge). Always enabled anytime the CP1Buffer E2 configuration bit is set. Each rising edge of PC clocks whatever data is read from CP1's output into its output register regardless of what other function is being performed by the PC pin. In certain modes listed above, the operation of CP1 in buffered mode combined with the need to clock its output using the PC pin, would interfere with or prevent the proper operation of some circuit function implementations.
PC Direct
Direct control of IA4 polarity via the PC pin, logic 0 = inverted, logic 1 = no inversion (external). Clamps OA2 to VREFout when PC is a logic 1, and has no effect when it's a logic 0 (external).
RS Flip-Flop
CP1 Direct
None. IA4 polarity control based directly on CP1 output, a logic 0 = inverted, logic 1 = no inversion (internal). Clocks CP1 data register (external).
PC Clock
"routing" switch has been made externally available for some unique device operating modes. The control is made through the external PC (polarity control) pin, or signals routed internally to this same input pin. See Table 4 for complete PC pin operation details. These comparator logic control/option modes are all configured within PAC-Designer to achieve the operation summarized in Table 4. More information is available in the online help file for PAC-Designer and in application notes that describe the circuits made possible by this onchip logic.
has been modified to include a slew-rate enhancement feature. This circuitry is not part of the output amplifier (OA) PACell and therefore does not change the specified slew rate as given in the data sheet. Rather, it enhances the operation of IA4 and improves its performance in applications such as a voltage controlled oscillators (VCO), thereby improving its performance in reproducing non-linear transfer functions. The ispPAC is shipped with this bit normally enabled. If identical operation between all IA PACells is desired, the SRE bit associated with IA4 can be disabled by selecting the appropriated edit symbol command in PAC-Designer and making the change.
IA4 Slew-Rate Enhancement
Because of the special applications addressed by the inclusion of a polarity control function in IA4, its circuitry
Multiplexer Input control of IA1
An external multiplexer select (MSEL) pin is provided that controls which of two possible input connections are
22
Specifications ISPPAC20
Theory of Operation (Continued)
Table 5. JTAG User Configuration Bits
Symbol DSthru Name Direct Serial Pass-Thru Description Used to enable the serial, JTAG/Direct mode. Enables addressing of DAC directly from the serial latches instead of the E2 cells. Overrides the effect of the DMode pin. Overridden itself by the ENSPI mode pin (high). Used to enable comparator hysteresis mode for both comparators (47mV). Selected in PAC-Designer by double clicking on the hysteresis symbol in between the two comparators or by using the edit symbol dialog. Used to disable the TDO output, or in other words place it in permanent high-impedance output mode. This is done to reduce unnecessary on-chip perturbation of the analog circuitry while changing the DAC codes in either the JTAG/E2 or JTAG/Direct modes. Has no effect on TDO when ENSPI is high and the DAC is in SPI mode. Note that TDO is disabled at certain times even when the DisTDO bit is not set. Used to control the various modes of PC (polarity control) digital input pin function. These include simple logic control of IA4's gain polarity, a blocking of the PC pin input altogether, an oscillator flip-flop control mode and gating of the oscillator flip-flop mode, and direct connection to CP1OUT. Used to enable either XOR or FF output mode on the Window output pin. Causes output of Comparator 1 (CP1) to be latched into a D-flip-flop before being output. Latch is updated by clocking the PC input pin. These bits are available to store information about an individual device in on-chip E2 configuration memory. For example, the configuration code, performance data or other classification data could be stored and later retrieved to identify some unique property associated by the user with the device. Disables all three comparator-related outputs (CP1, CP2 and Window) placing them in a high impedance state. The purpose of the option is to allow quieter operation of comparators (less effect on other analog circuitry) when their outputs are only required for on-chip operation. Normally on, this bit enhances the slew rate capability of IA4. Normally this is of greatest benefit in such applications as voltage controlled oscillators where an improvement in non-sinusoidal waveform generation is desired. Has no effect on THD of normal signals, but can still be disabled if output needs to be matched exactly to the characteristics of IA1-3. Setting this bit causes all subsequent readouts of the device configuration to be disabled (JTAG Verify commands). Can be reset by performing a JTAG user bulk erase command and reprogramming the device. This feature is used to prevent unauthorized readout of the device's configuration. Enables an external input reference to determine the output common-mode voltage of OA1 and/or OA2 instead of the normally-used 2.5V from on-chip.
CPHyst
Comparator Hysteresis
DisTDO
Disable TDO
PCMode1, 2
Polarity Control Mode
WCMode CP1Buffer UES1-7
Window Compare Mode Comparator 1 Latch Enable User Electronic Signature
CPOut
Comparator Output Disable
SRE
Slew Rate Enhancement
ESF
Electronic Security Fuse
EnCMVin1, 2 Enable External CMV Ref
routed to the input of IA1. When MSEL is a logic 0, input line "A" is selected to go to IA1, when it is a logic 1, input line "B" is used. This arrangement allows a number of applications to be implemented, from something as straight forward as two input signal channels, to more complex functions such as those provided for by the polarity control pin (with the option of different signals being used as well).
JTAG User Bits
There are a number of user configured E2 bits that control various aspects of ispPAC operation and can all be accessed in either the pull-down menus or directly in the schematic design entry screen of the PAC-Designer software. See the online help associated with the ISPPAC20 in PAC-Designer for more details of how to set/ program various operation modes. The list of control E2 bits available is given in Table 5.
23
Specifications ISPPAC20
Software-Based Design Environment Design Entry Software
Designers configure the ISPPAC20 and verify its performance using PAC-Designer, an easy to use, Microsoft Windows compatible program. Circuit designs are entered graphically and then verified, all within the PAC-Designer environment. Full device programming is supported using PC parallel port I/O operations and a download cable connected to the serial programming interface of the ISPPAC20. A library of configurations is included with basic solutions and examples of advanced circuit techniques. In addition, comprehensive on-line and printed documentation is provided that covers all aspects of PAC-Designer operation. The PAC-Designer schematic window, shown in Figure 13, provides access to all configurable ISPPAC20 elements via its graphical user interface. All analog input and output pins are represented. Static or non-configurable pins such as power, ground, VREFOUT, and the serial digital interface are omitted for clarity. Any element in the schematic window can be accessed via mouse operations as well as menu commands. When completed, configurations can be saved, simulated, and downloaded to devices. PAC-Designer operation can be automated and extended by using custom-designed Visual Basic(R) programs that set the interconnections and the parameters of ispPAC products. These stand-alone programs are called macros. An example of such a macro is the biquad filter generator supplied with PAC-Designer. With this macro, filter parameters such as gain, Q and corner frequency are input directly and then automatically converted to a schematic configuration. More information on this and other topics is included in the on-line documentation as well as the PAC-Designer Getting Started Manual.
Figure 13. Initial PAC-Designer Schematic Design Entry Screen
PAC Designer - [Design1]
File Edit View Tools Options Window Help
OUT1
MSEL = A
CPIN
1.07 pF IN1 a 1 IA1 b IN2 IA2 2.5V 1 IN3 1 IA3 OA2 2.5V 3V 1.5V DACOUT Code: 80h 0.0000V E2Cells/Parallel Inputs UES Bits = 0000000 PACblock 2 1.07 pF CP2 CP2OUT Digital outputs=enabled -1 OA1 PACblock 1 CP1
Direct
CP1OUT
Hyst=on
WINDOW XOR
3V 1.5V OUT2
IA4 -1
SRE=on
Polarity Control: PC pin
PC = 0
Ready
24
Specifications ISPPAC20
In-System Programmability Electronic Security
An electronic security "fuse" (ESF) bit is provided in every ISPPAC20 device to prevent unauthorized readout of the E2CMOS user bit patterns. Once programmed, this cell prevents further access to the functional user bits in the device. This cell can only be erased by reprogramming the device, so the original configuration can not be examined once programmed. Usage of this feature is optional.
Evaluation Fixture
Included in the basic ISPPAC20 Design Kit is an engineering prototype board that is connected to the parallel port of a PC. It demonstrates proper layout techniques for the ISPPAC20 and can be used in real time to check circuit operation as part of the design process. Input and output connections as well as a "breadboard" circuit area are provided to speed debugging of the circuit.
User Electronic Signature
A user electronic signature (UES) feature is included in the E2 memory of the ISPPAC20. It contains seven bits that can be configured by the user to store unique data such as ID codes, revision numbers or inventory control data.
Production Programming Support
Once a final configuration is determined, an ASCII format JEDEC file is created using the PAC-Designer software. Parts can then be ordered through the usual supply channels with the user's specific configuration already preloaded into the parts. By virtue of its standard interface, compatibility is maintained with existing production programming equipment giving customers a wide degree of freedom and flexibility in production planning.
Figure 14. Configuring the ISPPAC20 "In-System" from a PC Parallel Port
PAC-Designer Software
Other System Circuitry
ispDownload Cable (6') 4 ISPPAC20 Device
25
Specifications ISPPAC20
IEEE Standard 1149.1 Interface Serial Port Programming Interface
Communication with the ISPPAC20 is facilitated via an IEEE 1149.1 test access port (TAP). It is used by the ISPPAC20 as a serial programming interface, and not for boundary scan test purposes. There are no boundary scan logic cells in the ISPPAC20 architecture. This does not prevent the ISPPAC20 from functioning correctly, however, when placed in a valid serial chain with other IEEE 1149.1 compliant devices. A brief description of the ISPPAC20 serial interface follows. For complete details of the reference specification, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-1990 (which now includes IEEE Std 1149.1a-1993). out of the user register to verify the current ISPPAC20 configuration. Instructions exist to access all data registers and perform internal control operations. For compatibility between compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are functionally specified, but inclusion is strictly optional. Finally, there are provisions for optional data registers defined by the manufacturer. The two required registers are the bypass and boundary-scan registers. For ISPPAC20, the bypass register is a 1-bit shift register that provides a short path through the device when boundary testing or other operations are not being performed. The ISPPAC20, as mentioned, has no boundary-scan logic and therefore no boundary scan register. All instructions relating to boundary scan operations place the ISPPAC20 in the BYPASS mode to maintain compliance with the specification. The optional identification register described in IEEE 1149.1 is also included in the ISPPAC20. One additional data register included in the TAP of the ISPPAC20 is the Lattice defined user register. Figure 15 shows how the instruction and various data registers are placed in an ISPPAC20.
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the ISPPAC20. The TAP controller is a state machine driven with mode and clock inputs. Under the correct protocol, instructions are shifted into an instruction register which then determines subsequent data input, data output, and related operations. Device programming is performed by addressing the user register, shifting data in, and then executing a program user instruction, after which the data is transferred to internal E2CMOS cells. It is these non-volatile cells that determine the configuration of the ISPPAC20. By cycling the TAP controller through the necessary states, data can also be shifted Figure 15. ISPPAC20 TAP Registers
TAP Controller Specifics
The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a small 16-state controller design. In a given state, the controller responds according to the level on the TMS input as shown in Figure 16. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO) becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, Run-Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register, and Pause-Instruction-Register. But there is only one steady state for the condition when TMS is set high: the TestLogic-Reset state. This allows a reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on default state. When the correct logic sequence is applied to the TMS and TCK inputs, the TAP will exit the Test-Logic-Reset state and move to the desired state. The next state after Test-Logic-Reset is Run-Test/Idle. Until a data or instruction scan is performed, no action will occur in Run-Test/ Idle (steady state = idle). After Run-Test/Idle, either a data or instruction scan is performed. The states of the Data and Instruction Register blocks are identical to each other differing only in their entry points. When either block
User Register ID Register Bypass Register Instruction Register
Test Access Port (TAP) Logic
Output Latch
TDI
TCK
TMS
TRST
TDO
26
MUX
Specifications ISPPAC20
IEEE Standard 1149.1 Interface
is entered, the first action is a capture operation. For the Data Registers, the Capture-DR state is very simple: it captures (parallel loads) data onto the selected serial data path (previously chosen with the appropriate instruction). For the Instruction Register, the Capture-IR state will always load the IDCODE instruction. It will always enable the ID Register for readout if no other instruction is loaded prior to a Shift-DR operation. This, in conjunction with mandated bit codes, allows a "blind" interrogation of any device in a compliant IEEE 1149.1 serial chain. From the Capture state, the TAP transitions to either the Shift or Exit1 state. Normally the Shift state follows the Capture state so that test data or status information can be shifted out or new data shifted in. Following the Shift state, the TAP either returns to the Run-Test/Idle state via the Exit1 and Update states or enters the Pause state via Exit1. The Pause state is used to temporarily suspend the shifting of data through either the Data or Instruction Register while an external operation is performed. From the Pause state, shifting can resume by reentering the Shift state via the Exit2 state or be terminated by entering the Run-Test/Idle state via the Exit2 and Update states. If the proper instruction is shifted in during a Shift-IR operation, the next entry into Run-Test/Idle initiates the test mode (steady state = test). This is when the device is actually programmed, erased or verified. All other instructions are executed in the Update state.
Test Instructions
Like data registers, the IEEE 1149.1 standard also mandates the inclusion of certain instructions. It outlines the function of three required and six optional instructions. Any additional instructions are left exclusively for the manufacturer to determine. The instruction word length is not mandated other than to be a minimum of 2-bits, with only the BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respectively). The ISPPAC20 contains the required minimum instruction set as well as one from the optional instruction set. In addition, there are several proprietary instructions that allow the device to be configured and verified. For ISPPAC20, the instruction word length is 5bits. All ISPPAC20 instructions available to users are shown in Table 6.
BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and TDO and allows serial data to be transferred through the device without affecting the operation of the
Figure 16. Test Access Port (TAP) Contoller State Diagram
1 0 Test-Logic-Rst 0 Run-Test/Idle 1 1 Select-DR-Scan 0 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 0 1 Exit2-DR 1 Update-DR 1 0 1 0 0 0 1 1 1 Select-IR-Scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 0 0 0 1 1
Note: The value shown adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK.
27
Specifications ISPPAC20
IEEE Standard 1149.1 Interface
Table 6. ISPPAC20 TAP Instructions
Instruction EXTEST ADDUSR UBE VERUSR PRGUSR IDCODE ENCAL DBE VERDAC PRGDAC ADDDAC SAMPLE BYPASS Code 00000 00001 00010 00011 00100 01101 10000 10001 10010 10011 10100 11110 11111 Description External test. Default to BYPASS. Address user data register. User bulk erase. Verify user data register. Program user data register. Read identification data register. Enable calibration sequence. DAC bulk erase. Verify the DAC register. Program the DAC register. Address the DAC register. Sample/Preload. Default to BYPASS. Bypass (connect TDI to TDO).
TAP Inst/PAC20
Figure 17. Identification Code (IDCODE) 32-Bit Binary Word for Lattice ISPPAC20
MSB LSB
XXXX / 0000 0001 0001 0001 / 0000 0100 001 / 1
Part Number (16 bits) 0111h = PAC20
JEDEC Manfacturer Identity Code for Lattice Semiconductor (11 bits) Constant 1 (1 bit) per 1149.1-1990
Version (4 bits) E 2 Configured
ISPPAC20. The bit code of this instruction is defined to be all ones by the IEEE 1149.1 standard. The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI and TDO. The ISPPAC20 has no boundary-scan register, so for compatibility it defaults to the BYPASS mode whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown in Table 6. The EXTEST (external test) instruction is required and would normally place the device into an external boundary test mode while also enabling the Boundary-Scan Register to be connected between TDI and TDO. Again, since the ISPPAC20 has no boundary-scan logic, the device is put in the BYPASS mode to ensure specification compatibility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros. The optional IDCODE (identification code) instruction is incorporated in the ISPPAC20 and leaves it in its functional mode when executed. It selects the Device Identification Register to be connected between TDI and TDO. The Identification Register is a 32-bit shift register containing information regarding the IC manufacturer, device type and version code (see Figure 17). Access to the Identification Register is immediately available, via a TAP data scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this instruction is defined by Lattice as shown in Table 6.
ADDUSR (address user register) instruction is a Lattice defined instruction that selects the user register to be shifted during a Shift-DR operation. Normal operation of a device is not interrupted by this instruction. It precedes a PROGUSR (program user) instruction to shift in a new configuration and follows a VERUSR (verify user) instruction to shift out the current configuration. The bit code for this instruction is shown in Table 6.
The PRGUSR (program user) is a Lattice instruction that enables the data shifted into the user register to be programmed into the non-volatile E2CMOS memory of the ISPPAC20 and thereby alter its configuration. The user register is a 109-bit shift register that contains all the user-controlled parametric and interconnect data pertaining to the configuration of the ISPPAC20. Normal operation of the device is interrupted during the actual programming time. A programming operation does not begin until entry of the Run-Test/Idle state. The time required to insure data retention is given in the TAP signal specifications table. The user must ensure that the recommended programming times are observed. The bit code for this instruction is shown in Table 6.
VERUSR (verify user) is the next Lattice instruction and causes the current configuration of the ISPPAC20 to be loaded into the user register. This operation doesn't interrupt operation of the device. The current configuration can then be shifted out of the user register immediately after an ADDUSR instruction is executed. The bit code for this instruction is shown in Table 6.
For DAC operations, the ADDDAC (address DAC), PRGDAC (program DAC), VERDAC (verify DAC) and DBE (DAC bulk erase, instructions are provided. They have basically the same effect as the "user" instructions
28
Specifications ISPPAC20
IEEE Standard 1149.1 Interface
except that they only affect the contents of the DAC register. The bit codes for these instructions are shown in Table 6. proceeds a PRGUSR operation, otherwise one to zero changes would not be implemented. It can also be used to erase all configuration information from a device and is the default condition of parts shipped from the factory. The same programming constraints apply to UBE as for PRGUSR. The bit code for this instruction is shown in Table 6. The ADDUSR, BYPASS, EXTEST, IDCODE and SAMPLE/PRELOAD instructions are all executed in the Update-IR state. Other instructions: PRGUSR, VERUSR and UBE are executed upon entry of the Run-Test/Idle state. It is recommended that when all serial interface operations are completed, the TAP controller be reset and left in the Test-Logic-Reset state (the power-up default) and the TCK and TMS inputs idled. This will insure the best analog performance possible by minimizing the effects of digital logic "feed-through."
ENCAL (enable calibration) is a Lattice instruction that enables the start of an auto-calibration sequence. This operation causes all outputs of the device to go to 0V until the calibration sequence is completed (see timing specifications). As with the programming instructions above, calibration does not begin until entry of the Run-Test/Idle state. The completion of the calibration is not dependent, however, on any further TAP control. This means the state of the TAP can be returned immediately to the TestLogic-Reset state. The only consideration would be to not clock the TAP during critical analog operations. The first several milliseconds of the calibration routine are consumed waiting for configurations to settle, though, leaving more than enough time to clock the TAP back to the Test-Logic-Reset state. The bit code for this instruction is shown in Table 6.
The last Lattice instruction is UBE (user bulk erase). Operation of the device is interrupted during UBE, after which all inputs are disconnected and all outputs driven to VCOM (2.5V). To economize internal circuitry, programming can only be selectively done in one direction (from zeroes to ones). The UBE is used to return all user bits to a zero state at the same time. A UBE usually
29
Specifications ISPPAC20
Package Diagrams
44-Pin Plastic PLCC Dimensions in Inches MIN./MAX. (Dimensions in millimeters, shown in parenthesis, are for reference only)
0.020 (.51) Minimum 0.050 (1.27) BSC Pin 1 0.013 (0.33) 0.021 (0.53) Top View 0.026 (0.66) 0.032 (0.81) 0.590 (14.99) 0.630 (16.00)
0.042 (1.07) x 45 0.048 (1.22)
0.650 (16.51) 0.656 (16.66) 0.685 (17.40) 0.695 (17.65) 0.165 (4.19) 0.180 (4.57) Seating Plane Coplanarity not to exceed 0.004 (.102)
0.090 (2.29) 0.120 (3.05)
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